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W83194BR-250
STEPLESS CLOCK FOR VIA PRO266 CHIPSET
W83194BR-250 Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. 02/Apr 1.0 Dates Version Version On Web n.a. 1.0 All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Main Contents
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
1.0
GENERAL DESCRIPTION
The W83194BR-250 is a Clock Synthesizer for VIA Pro266 chipset. W83194BR-250 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, PCI, AGP, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-250 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. The W83194BR-250 provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also the skew of CPU and AGP clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-250 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2.0
* * * * * * * * * * * *
PRODUCT FEATURES
4 CPU clocks 3 AGP for chipset and AGP clocks 9 PCI synchronous clocks. Optional single or mixed supply: (VddR = VddP= Vdd48 = VddA =Vdd = 3.3V, VddLAPIC=VddLCPU=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200 MHz I2C 2-Wire serial interface and I2C read back 0.25% and 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes 48 MHz for USB 24 MHz for super I/O 48-pin SSOP package
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
3.0
PIN CONFIGURATION
VddR Vss Xin Xout Vdd48 48MHz/ FS3* 24_48MHz/FS2* Vss PCICLK_F/Mode1* PCICLK1 PCICLK2 Vss PCICLK3 PCICLK4 VddP PCICLK5 PCICLK6 PCICLK7 Vss PCICLK8 FS1* FS0* AGP0 VddA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0 REF1/*FS4 VddLAPIC IOAPIC0 IOAPIC1 Vss CPUCLK_F VddLCPU Vss CPUCLK1 CPUCLK2 VddLCPU Vss CPUCLK3 CPU_STOP# PCI_STOP#/RESET$ PD# Vdd Vss SDATA* SDCLK* AGP2 AGP1 Vss
*: internal pull-up #: active low $: ope drain
4.0
PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
4.1 Crystal I/O
SYMBOL Xin Xout PIN 3 4 I/O IN OUT FUNCTION Crystal input with internal loading capacitors(36pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors(36pF).
4.2 CPU, AGP,PCI,IOAPIC Clock Outputs
SYMBOL CPUCLK_F , [1:3] PIN 42,39,38,35 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. CPUCLK_F is the free running pin and does not affect by CPU_STOP# CPU_STOP# when driven low. Pin9 *Mode1=1, PCI_STOP# when driven low. Pin9 *Mode1=0, RESET# output (4ms low active pulse when Watch Dog time out) Power Down mode when driven low. Clock outputs synchronous with PCI clock and powered by VddLAPIC. 3.3V 33MHz free running PCI clock during normal operation. Latched input for Mode1* at initial power up for pin34 selection. *Mode1=1, pin 34 =CPU_STOP# when driven low. *Mode1=0, pin 34 = RESET# output (4ms low active pulse when Watch Dog time out) Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset. H/W selecting the output frequency of CPU, AGP and PCI clocks (Default=1).
CPU_STOP# PCI_STOP#/RESET$
34 33
IN I/O
PD# IOAPIC[0:1] PCICLK_F/Mode1*
32 45,44 9
IN OUT I/O
PCICLK[1:8] AGP [0:2] *FS[1:0]
10,11,12,13,14 ,16,17,18,20 23,26,27 21,22
OUT OUT IN
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
4.3
I2C Control Interface
SYMBOL PIN 29 28 I/O I/O IN
2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface
SDATA* SDCLK*
4.4 Fixed Frequency Outputs
SYMBOL REF0 REF1 / *FS4 PIN 48 47 I/O OUT I/O FUNCTION 3.3V 14.318MHz reference clock. 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU, AGP and PCI clocks (Default=1). 24_48MHz/FS2* 7 I/O 24MHz or 48MHz output clock. Latched input for FS42at initial power up for H/W selecting the output frequency of CPU, AGP and PCI clocks (Default=1). 48MHz_1/ FS3* 6 I/O 48MHz / Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, AGP and PCI clocks (Default=1).
4.5 Power Pins
SYMBOL VddLCPU,VddLAPIC Vdd48 VddA VddP VddR Vdd Vss PIN 37,41,46 5 24 15 1 31 FUNCTION Power supply for CPU & IOAPIC, 2.5V or 3.3V. Power supply for 48MHz output,3.3V. Power supply for 3V_66 output, 3.3V. Power supply for PCICLK, 3.3V. Power supply for REFX2, 3.3V. Power for I2C CLK and DATA.
2,8,12,19,25,30,36, Circuit Ground. 40,43
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
5.0 FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 CPU(MHz) 200.0 190.0 180.0 170.0 166.0 160.0 150.0 145.0 140.0 136.0 130.0 124.0 66.8 100.2 118.0 133.4 66.8 100.2 115.0 133.4 66.8 100.2 110.0 133.4 105.0 90.0 85.0 78.0 66.8 100.2 75.0 133.4 AGP(MHZ) 66.7 63.3 60.0 68 66.4 64.0 75.0 72.5 70.0 68.0 65.0 62.0 66.8 66.8 78.7 66.7 66.8 66.8 76.7 66.7 66.8 66.8 73.3 66.7 70.0 60.0 56.7 78.0 66.8 66.8 75.0 66.7 PCI(MHz) IOAPIC 33.3 16.7 31.7 15.85 30.0 15 34 17 33.2 16.6 32.0 16 37.5 18.75 36.3 18.15 35.0 17.5 34.0 17 32.5 16.25 31.0 15.5 33.4 16.7 33.4 16.7 39.3 19.6 33.4 16.7 33.4 16.7 33.4 16.7 38.3 19.15 33.4 16.7 33.4 16.7 33.4 16.7 36.7 18.35 33.4 16.7 35.0 17 30.0 15 28.4 14.2 39.0 19.5 33.4 16.7 33.4 16.7 37.5 18.75 33.4 16.7
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
6.2.1 Register 0 : Frequency Select Register (default = 0)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = Normal 1 = Spread Spectrum enabled SSEL2 (for frequency table selection by software via I2C) SSEL1 (for frequency table selection by software via I2C) SSEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 6:4, Bit2 SSEL4 (for frequency table selection by software via I2C) SSEL3 (for frequency table selection by software via I2C) 0 = Running 1 = Tristate all outputs
6.2.2 Register 1
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1
: CPU Clock Register (1 = enable, 0 = Stopped)
Pin 44 45 47 48 35 38 39 42 Description IOAPIC1 (Active / Inactive) IOAPIC0 (Active / Inactive) REF1 (Active / Inactive) REF0 (Active / Inactive) CPUCLK3 (Active / Inactive) CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive)
6.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 20 18 17 16 14 13 11 10 PCICLK8 (Active / Inactive) PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) Description
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
6.2.4 Register 3: 24MHz, 48MHz Clock Register ( 1 = enable, 0 = Stopped )
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 1 1 1 1 1 Pin 6 7 9 27 26 23 Description 1 = 0.25% ,0=0.5% Spread Spectrum Modulation SEL24_48 (0=24Mhz, 1=48MHz) 48MHz (Active / Inactive) 24_48MHz (Active / Inactive) PCICLK_F (Active / Inactive) AGP2 (Active / Inactive) AGP1 (Active / Inactive) AGP0 (Active / Inactive)
6.2.5 Register 4: Buffer Chip Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @PowerUp Pin Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Description
6.2.6 Register 5: Buffer Chip Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @PowerUp Pin Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Reserved for W83176R-251 Description
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
6.2.7 Register 6: Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 X 0 0 0 0 0 0 Pin Enable Count Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0
6.2.8 Register 7:
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 0 0 0 0 0
M/N Program Register
Pin N value bit 8 Test 1(Please do not modify) Test 0 (Please do not modify) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 Description
6.2.9 Register 8: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
6.2.10 Register 9: Spread Spectrum Programming Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 Description
6.2.11 Register 10: Divisor and Step-less Enable Register
Bit 7 @PowerUp 0 Pin Description 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M Reserved Ratio SEL2 Ratio SEL1 Ratio SEL 0 CPU to AGP Skew 2 CPU to AGP Skew 1 CPU to AGP Skew 0
6 5 4 3 2 1 0
0 X X X 1 0 0
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6.2.12 Register 11: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 0 0 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID
(Read Only)
Description
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
6.2.13 Register 12:
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 0 0 0 0 1
Winbond Chip ID Register
Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID
(Read Only)
Description
Reg10 Reg10 Reg10 VCO/ VCO/ Bit5 bit4 bit3 CPU AGP SEL2 SEL1 SEL0 ratio ratio 0 0 0 2 4 0 0 1 2 5 0 1 0 2 6 0 1 1 3 6 1 0 0 4 4 1 0 1 4 6 1 1 0 6 6 1 1 1 X X
VCO/ PCI ratio 4 5 6 4 2 3 2 X
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
7.0
ORDERING INFORMATION
Part Number W83194BR-250 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
8.0
HOW TO READ THE TOP MARKING
W83194BR-250 28051234 814GAB
1st line: Winbond logo and the type number: W83194BR-250 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date:April. 2002 Revision 1.0
W83194BR-250
9.0
PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date:April. 2002 Revision 1.0

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